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| unisonic technologies co., ltd U74HCT7046 cmos ic www.unisonic.com.tw 1 of 16 copyright ? 2012 unisonic technologies co., ltd qw-r502-851.a phase locked loop with vco & lock detector ? description the U74HCT7046 is phase-locked-loop circuit that comprise a linear voltage-controlled oscillator (vco), two-phase comparators (pc1, pc2), a lock detector, a common signal input amplifier and a common comparator input. the lock detector capacitor should be connected between pin 15(cld) and pin 8(gnd).for a frequency range of 100khz to 10mhz,the lock detector capacitor must be 1000pf to 10pf,respectively. the signal can be directly coupled to large voltage signals, or with a series capacitor coupled to small signals. small voltage signals can be kept within the linear region of the input amplifiers with a self-bias input circuit. the U74HCT7046 and a passive low-pass filter form a second-order loop pll. with a linear op-amp, the vco achieves excellent linearity. the vco requires external capacitor and resistor. r1 (between r1 and gnd) and capacitor c1 (between c1a and c1b) determine the frequency range of the vco. r2 (between r2 and gnd) enables the vco to have a frequency offset if required. for the high input impedance of the vco, the design of low-pass filters is si mplified, and the designer has a wide choice of resistor/capacitor ranges. at pin 10 (dem out ), a demodulator output of t he vco input voltage is provided in order not to load the low-pass filter. in conventional techniques, the dem out voltage is one threshold voltage lower than the vco input voltage, but the dem out voltage of U74HCT7046 equals the vco input voltage. when dem out is used, a load resistor (rs) should be connected from dem out to gnd; but if unused, dem out should be left open. the vco output (vco out ) can be connected directly or via a frequ ency-divider to the comparator input (comp in ). if the vco input is held at a constant dc level, the vco output signal has a duty factor of 50% (maximum expected deviation 1%). a lo w level at the inhibit input (inh) enables the vco and demodulator, while a high level turns both off to mini mize standby power consumption. ? features * operating power supply voltage range: digital section 4.5 to 5.5 v vco section 4.5 to 5.5 v * up to 18 mhz (typ.) centre frequency at v cc = 5v * excellent v co frequency linearity * vco-inhibit control for on/off keying and for low standby power consumption * minimal frequency drift * zero voltage offset due to op-amp buffering
U74HCT7046 cmos ic unisonic technologies co., ltd 2 of 16 www.unisonic.com.tw qw-r502-851.a ? ordering information ordering number package packing lead free halogen free U74HCT7046l-s16-r U74HCT7046g-s16-r sop-16 tape reel U74HCT7046l-s16-t U74HCT7046g-s16-t sop-16 tube U74HCT7046l-p16-r U74HCT7046g-p16-r tssop-16 tape reel U74HCT7046l-p16-t U74HCT7046g-p16-t tssop-16 tube U74HCT7046 cmos ic unisonic technologies co., ltd 3 of 16 www.unisonic.com.tw qw-r502-851.a ? pin configuration ld pc1 out comp in vco out inh c1a c1b gnd v cc cld sig in pc2 out r2 r1 dem out vco in 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ? pin description pin no symbol function 1 ld lock detector output(active high) 2 pc1 out phase comparator 1output 3 comp in comparator input 4 vco out vco output 5 inh inhibit input 6 c1 a capacitor c1 connection a 7 c1 b capacitor c1 connection b 8 gnd ground(0v) 9 vco in vco input 10 dem out demodulator output 11 r1 resistor r1 connection 12 r2 resistor r2 connection 13 pc2 out phase comparator 2 output 14 sig in signal input 15 c ld lock detector capacitor input 16 v cc positive supply voltage U74HCT7046 cmos ic unisonic technologies co., ltd 4 of 16 www.unisonic.com.tw qw-r502-851.a ? logic symbol ? iec symbol U74HCT7046 cmos ic unisonic technologies co., ltd 5 of 16 www.unisonic.com.tw qw-r502-851.a ? logic diagram U74HCT7046 cmos ic unisonic technologies co., ltd 6 of 16 www.unisonic.com.tw qw-r502-851.a ? absolute maximum ratings parameter symbol test conditions min typ max unit dc supply voltage v cc -0.5 +7 v dc input diode current i ik for v in < ? 0.5v or v in >v cc +0.5v 20 ma dc output diode current i ok for v out < ? 0.5v or v out >v cc +0.5v 20 ma dc output source or sink current i o for ? 0.5v U74HCT7046 cmos ic unisonic technologies co., ltd 8 of 16 www.unisonic.com.tw qw-r502-851.a ? phase comparators . if the signal swing is between the standard hc family input logic levels, the signal input (sig in ) can be directly coupled to the self-biasing amplifier at pin 14. capacitive coupling is required for signals with smaller swings. phase comparator 1 (pc1) this is an exclusive-or network. to obtain the maxi mum locking range, the signal and comparator input frequencies (f i ) must have a 50% duty factor. the transfer characteristic of pc1, assuming ripple (f r = 2f i ) is suppressed, is: ) ( v v compin sigin demout cc ? = where v demout is the demodulator output at pin 10; v demout = v pc1out (via low-pass filter). the phase comparator gain is: ) r v / ( v k cc p = as shown in fig.1, the aver age output voltage from pc1, fed to the vc o input via the low-pass filter and seen at the demodulator out put at pin 10 (v demout ) is the resultant of the pha se differences of signals (sig in ) and the comparator input (comp in ). the average of v demout is equal to v cc /2 when there is no signal or noise at sig in and with this input the vco osc illates at the centre frequency (f o ). as shown in fig.2 it is the typical waveforms for the pc1 loop locked at f o . sig in comp in vco out pc1 out vco in v cc gnd fig.2 typical waveforms for pll using phase comparator 1, loop locked at f o . the frequency capture range (2f c ) is he frequency range of input signals on which the pll will lock if it was initially out-of-lock. the frequency lock range (2f l ) is the frequency range of input signals on which the loop will stay locked if it was initially in lock. the capture range is smaller or equal to the lock range. with pc1, the low-pass filter charac teristics determine the capture ran ge which can be made as large as the lock range. this configuration retains lock even with very noisy i nput signals. typical behavior of this type of phase U74HCT7046 cmos ic unisonic technologies co., ltd 9 of 16 www.unisonic.com.tw qw-r502-851.a comparator is that it can lock to input frequencies close to the harmonics of the vco centre frequency. U74HCT7046 cmos ic unisonic technologies co., ltd 10 of 16 www.unisonic.com.tw qw-r502-851.a ? phase comparators (cont.) phase comparator 2 (pc2) this is a positive edge-triggered phase and frequency detect or. if the pll is using the comparator, the loop is controlled by positive signal transit ions and the duty factors of sig in and comp in are not important. pc2 is comprised of two d-type flip-flops, control-gating and a 3- state output stage. t he circuit function is as an up-down counter (logic diagram) for sig in causes an up-count and comp in causes a down-count. the transfer function of pc2, assuming ripple (f r = f i ) is suppressed, is ) ( 4 v v compin sigin demout cc ? = where v demout is the demodulator output at pin 10; v demout = v pc2out (via low-pass filter). the phase comparator gain is: ) r v / ( 4 v k cc p = as shown in fig.3, v demout is the resultant of the in itial phase differences of sig in and comp in . typical waveforms for the pc2 loop locked at f o are shown in fig.4. 4 fig.3 phase comparator 2: average output voltage versus input phase difference. fig.4 typical waveforms for pll using phase comparator 2, loop locked at f o . U74HCT7046 cmos ic unisonic technologies co., ltd 11 of 16 www.unisonic.com.tw qw-r502-851.a ? phase comparators (cont.) if the frequencies of sig in and comp in are equal but the phase of sig in leads that of comp in , the p-type output driver at pc2 out is held ?on? for a time corresponding to the phase difference ( demout ). if the phase of sig in lags that of comp in , the n-type driver is held ?on?. if the frequency of sig in is higher than that of comp in , the p-type output driver is held ?on? for most of the input signal cycle time, and for the remainder of the cy cle both n and p-type drivers are ?off? (3-state). if the frequency of sig in is lower than that of comp in , the n-type driver that is held ?o n? for most of the cycle. then the voltage at the capacitor (c2) of the low-pass filter connected to pc2 out varies until the signal and comparator inputs are equal in both phase and frequency. at this stable state the voltage on c2 re mains constant as the pc2 output is in 3-state and the vco input at pin 9 is a high impedance. also in the conditi on, the signal at the phase comparator pulse output (pcp out ) is a high level, and it indicates a locked condition. for pc2, there is no phase difference between sig in and comp in over the full frequency range of the vco. and as the low-pass filter, the power dissipation is reduced because both p and n-type drivers are ?off? for most of the signal input cycle. it should be noted that the pll lock range for this type of phase comparator is equal to the capture range and this is independent of the low-pass filter. the vco adjusts to its lowest frequency via pc2 when no signal present at sig in . ? lock detector theory of operation detection of a locked condition is accomplished by a nor gate and an envelope detec tor.when the pll is in lock, the output of the no r gate is high and the lock detector output (pin 1) is at a constant high level. as the loop tracks the signal on pin 14 (s ignal in), the nor gate output s pulses whose widths repres ent the phase differ-ences between the vco and the input signal. the time between pulse s will be approximately equal to the time constant of the vco center frequency. during the rise time of the pulse, the diode across the 1.5k ? resistor is forward biased and the time constant in the path that charges the lock det ector capacitor is t = (150 ? x cld). during the fall time of the pulse the capacitor discharges through the 1.5k ? and the 150 ? resistors and the channel resistance of the n-device of the nor gate to ground (t = (1.5k ? + 150 ? + rn-channel) x cld). the waveform preset at the capacitor resembles a sawt ooth.the lock detector capacitor value is determined by the vco center frequency. the typical range of capacito r for a frequency of 10mhz is about 10pf and for a frequency of 100khz is about 1000pf. as long as the loop remains locked and tracking, the level of the sawtooth will not go below the switching threshold of the schmitt-trigger inverter. if the loop breaks lock, the width of the error pulse will be wide enough to allow the sawtooth waveform to go below threshold and a level change at the output of the schmitt trigger will indicate a loss of lo ck. the lock detector capacitor also acts to lter out small glitches that can occur when the loop is either seeking or losing lock. ? figure references for dc characteristics self-bias operating point v in i in v in fig.7 typical input resistance curve at sig in , comp in . U74HCT7046 cmos ic unisonic technologies co., ltd 12 of 16 www.unisonic.com.tw qw-r502-851.a ? ac waveforms fig.8 waveforms showing input (sig in , comp in ) to output (pc1 out ) propagation delays and the ou tput transition times. fig.9 waveforms showing the 3-state enable and disable times for pc2 out . U74HCT7046 cmos ic unisonic technologies co., ltd 13 of 16 www.unisonic.com.tw qw-r502-851.a ? ac waveforms(cont.) fig.10 definition of vco frequency linearity: ? v = 0.5 v over the vcc range: for vco linearit y f ? 0 = (f 1 +f 2 )/2, linearity (f ? 0 +f 0 )/f ? 0 100% U74HCT7046 cmos ic unisonic technologies co., ltd 14 of 16 www.unisonic.com.tw qw-r502-851.a ? application information this is a reference for the values of external components to be used with the U74HCT7046 in a pll system. the ranges of the val ues of the components: vco frequency without extra offset (phase comparator: pc1, pc2) frequency characteristic: with r2 = and r1 between 3 k ? and 300 k ? , the characteristics of the vco operation will be as shown in fig.11 (due to r1, c1 time constant a small offset remains when r2= ). fig.11 frequency characteristic of vco operating without offset: f 0 = centre frequency; 2f l = frequency lock range. component value r1 3 k ? ~ 300 k ? r2 3 k ? ~ 300 k ? r1+r2 parallel value > 2.7 k ? c1 greater than 40 pf U74HCT7046 cmos ic unisonic technologies co., ltd 15 of 16 www.unisonic.com.tw qw-r502-851.a ? application information(cont.) vco frequency with extra offset (phase comparator: pc1, pc2) frequency characteristic: with r1 and r2 between 3 k ? and 300 k ? , the characteristics of the vco oper ation will be as shown in fig.12. due to r1, c1 f vco f max f 0 f min ? v cc v cc ?0.9v v cc vco in 0.9v 2f l f off due to r2, c1 fig.12 frequency characteristic of vco operating with offset: f 0 = centre frequency; 2f l = frequency lock range. pc1, pc2 selection of r1, r2 and c1 given f o and f l , determine the value of r1 c1 calculate f off from the equation f off = f o ? 1.6f l obtain the values of c1 and r2 calculate the value of r1 fr om the value of c1 and r1 c1. subject phase comparator design considerations pll conditions with no signal at the sig in input pc1 vco adjusts to f o with demout = 90 and v vconin = 1/2 v cd (fig.1). pc2 vco adjusts to f o with demout = -360 and v vconin = min. (fig.3). U74HCT7046 cmos ic unisonic technologies co., ltd 16 of 16 www.unisonic.com.tw qw-r502-851.a ? application information(cont.) pll frequency capture range (phase comparator: pc1, pc2) loop filter component selection j a small capture range (2f c ) is obtained if / f 2 1 f 2 l c fig.13 simple loop lter for pll without offset; r3 500 ? . r3 c2 input output 1/ 3 m ) ( f j (b) amplitude characteristic (c) pole-zero diagram + = fig.14 simple loop lter for pll with offset; r3 + r4 500 ? . subject phase comparator design considerations pll locks on harmonics at centre frequency pc1 yes pc2 no noise rejection at signal input pc1 high pc2 low ac ripple content when pll is locked pc1 f r = 2f i , large ripple content at demout = 90 pc2 f r = f i , small ripple content at demout = 0 utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. |
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